In recent years, for image compression in a display interface or a camera interface or image compression in a bus inside SoC (System-on-a-Chip), one pixel is input into a compressor per cycle and an expander has to expand one pixel per cycle, and thus high throughput is required. Such image compression requires a small circuit scale, but compression in units of block such as H.264 requires a large circuit scale and thus DPCM (Differential Pulse Code Modulation) based compression taking a differential relative to a predictive value in units of pixel is employed. In order to realize a high compression rate in DPCM based compression, an accuracy of predicting a predictive value needs to be increased and it is important to provide many predictive modes.
With a conventional technique, however, there is a problem that if many predictive modes are provided for DPCM in order to realize throughput at one pixel per cycle, an operation frequency of a compressor does not increase. That is, local decode pixels required for a predictive mode determination processing on a pixel to be next compressed have to be generated within one cycle, but a pulse circuit delay thereof is large and thus the operation frequency does not easily increase.